Beyond Silicon 2026: The Future of Computing

This talk introduces Quandela's photonic quantum computing platform and covers both the quantum processors (QPUs) currently in use and the roadmap towards fault-tolerant quantum computing (FTQC). The basics of photonic architectures, current experimental and technological advances and access to these systems via cloud infrastructures are explained.

In the further course, application classes are considered that can be addressed with photonic quantum systems available in the short term, with a special focus on hybrid approaches that combine quantum computing and artificial intelligence. It will be shown how quantum machine learning methods can use photonic processors in conjunction with classical methods to enable new computing paradigms, and concrete application examples and current developments in the field of hybrid quantum AI will be presented.

At Nuremberg Institute of Technology, we develop processes for the design, simulation and manufacture of micro-optical elements using multiphoton polymerization and femtosecond laser material processing.

The know-how for manufacturing optical interfaces between PICs, single-mode fibers and quantum computers can be transferred from quantum optical applications to a wider range of applications, such as photonic chip architectures.

Modern computers are still shackled by the Von Neumann bottleneck, the incessant congestion of data between processor and memory that limits the speed and efficiency of machine thinking. Optical computing breaks through this barrier by replacing electronic transistors and memory with their photonic counterparts, allowing data to be stored and processed in the form of light. This combination of optical memory and digital optical logic system unlocks the true potential of symbolic reasoning, the structured, rule-based intelligence that goes beyond today's AI.

As digital transformation accelerates across industries, fiber optic networks have become the backbone of modern business communications and critical infrastructure - including power grids, financial systems, transportation networks, healthcare and telecommunications. Their enormous bandwidth, low latency and physical properties make them the preferred medium for high-speed data transmission over long distances. But as dependence on these networks grows, so does the urgency to protect them from an expanding threat landscape, including the most drastic challenge on the horizon: the rise of quantum computing.

For more than a decade, neuromorphic chip developers and application engineers have been striving to find and bring to market the "killer app" for neuromorphic technologies. With the advent of commercial neuromorphic neural accelerators and neuromorphic sensors, awareness and adoption have increased, but not adoption. Identifying vulnerabilities in current systems, improving SW and HW interfaces for improved interoperability of neuromorphic technology, and robust benchmarks are finally paving the way for industrial adoption of neuromorphic technology. Based on several success stories, we present a possible "recipe" for the development of reference designs, the next step towards a pragmatic and optimized integration of neuromorphic sensing and data processing in industrial applications.

Neuromorphic computing and spiking neural networks have long been an academic topic, as no hardware was available for industrial applications. The recent availability of commercial hardware has sparked interest in this particularly energy and latency efficient technology. A collection of project results with high industrial relevance and strong neuromorphic suitability is presented, spanning the fields of automotive, robotics, sports, space, telecommunications and art.

The AI accelerators available on the market in the classic von Neumann architecture, for example for edge sensorics and edge computing, process digital data, consume more than 90% of the energy for data exchange between the processor and memory unit and are not real-time capable. Compared to classic AI accelerators, AI accelerators with the memory unit very close to the processor have a 30% reduction in energy consumption and reduced latency.
However, solving the problem of the exponential global increase in data volumes and the associated computing power as well as the increasing complexity of AI training algorithms requires further fundamental breakthroughs in the hardware for AI accelerators. For example, ReRAM memristor Xbars are used in new AI accelerators. Memristors are reconfigurable, non-volatile memory cells that can be used, for example, to simulate the function of weights in neural networks.
The analog BFO memristor presented here [1-5] is one of the few memristors with continuous memory and temporally separated read and write operations for data storage and processing in the same memristor cell [6]. It is discussed why BFO memristors are promising for low-power, low-latency AI accelerators, such as autonomous driving, surveillance, and robotics.

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2) T. You, Y. Shuai, W. Luo, N. Du, D. Bürger, I. Skorupa, R. Hübner, S. Henker, C. G. Mayr, R. Schüffny, T. Mikolajick, O.G. Schmidt, H. Schmidt, Adv. Funct. Mat. 24, 3357-3365 (2014).
3) N. Du, M. Kiani, C.G. Mayr, T. You, D. Bürger, I. Skorupa, O.G. Schmidt, H. Schmidt, Front. Neurosci. 9, 227 (2015).
4) N. Du, X. Zhao, Z. Chen, B. Choubey, M. Di Ventra, I. Skorupa, D. Bürger, H. Schmidt, Front. Neurosci. 15, 660894 (2021).
5) S. V. Vegesna, V. R. Rayapati, H. Schmidt, Phys. Rev. Applied 22, 034028 (2024).
6) H. Schmidt, J. Appl. Phys. 135, 200902 (2024).

A smartphone in standby mode consumes more energy than the brain, which de facto easily performs calculations that put a lot of strain on a conventional computer chip. In view of the enormous amount of energy that current generative AI models now consume, the question arises as to whether biological systems can solve such tasks efficiently. Reply is working with Cortical Labs and the University of Milan to gain practical experience with this computational method. Based on these findings, we will present the technical structure of the device and explain how to access the neuronal activity of the chip. We will also present the training paradigm and report on our experiences with learning the game "Pong". The results have raised doubts in our mind whether learning is the most promising and obvious application. Therefore, we propose an approach to use the system as an interface for processing biological data.