Workshop
Workshop Series: RISC-V – From Open Source to Custom CPU
12. October 2026 - 27. October 2026
KI-generiert mit ChatGPT (Quelle: Fraunhofer IIS),
RISC-V opens up new possibilities for innovative hardware systems and custom processor solutions. In this five-day workshop organized by Strategische Partnerschaft Sensorik e.V. / Cluster Sensorik in cooperation with the Bavarian Chips Alliance, you’ll gain a hands-on introduction to the development of modern RISC-V systems and build targeted expertise in embedded systems and chip design. You will learn about current development processes, expand your technological understanding, and gain practical experience in a forward-looking field of high strategic importance.
The workshop series will take place over five sessions, each from 9:00 a.m. to 5:00 p.m.
- October 12, 2026: RISC-V instruction set architecture | Tools (Docker, Make, compiler, simulator) | Setting up an open, embedded 32-bit RISC-V core & building a functional RISC-V-based system
- October 13, 2026: Compiling & Simulating a Matrix Multiplication in C | Profiling
- October 14, 2026: AI Acceleration | Development & Simulation
- October 26, 2026: RISC-V Extension Interface | MatMul ISA Extension | C Code for Interacting with the Accelerator
- October 27, 2026: Execution of the Industrial Application Program | Synthesis, Execution, and Verification of the Hardware for the FPGA
- Proficiency in the RISC-V development process (open instruction set architecture, microarchitecture, implementation on FPGAs) | Design, configuration, and use of RISC-V systems
- Analysis of performance bottlenecks
- Simulation and implementation of an AI accelerator for the independent further development of application-specific hardware architectures
- Fundamentals of the Central Processing Unit and explanations of the Instruction Set Architecture
- Application of a hardware description language—specifically SystemVerilog
- Integration of a single-cycle RISC-V CPU on a Field-Programmable Gate Array (FPGA)
The workshop is intended for professionals in the fields of embedded systems, digital IC design, and computer architecture who wish to gain practical experience with RISC-V and FPGA-based hardware development. A basic knowledge of HDL—particularly SystemVerilog—and computer architecture is recommended.
A meal allowance of €150.00 (net) per person will be charged for the five-day seminar. Travel to and from the seminar, as well as any overnight stays, are at the participant’s own expense; there are no other costs.
The workshop will be conducted in English.
For more information on the terms of participation and the registration form, please visit: www.sensorik-bayern.de/seminare/#chipdesign
Please note the separate compliance requirements of Fraunhofer IIS on that page.
