Event

SuSI Summit 2026 - Exploring ways to Chiptainability

7. Oktober 2026

08:00 - 17:00 Uhr

Infineon Technologies AG
Am Campeon, 1-15
85579 München-Neubiberg
Deutschland
In Google Maps anzeigen

Ein Wafer, umgeben von Nachhaltigkeitssymbolen AI-Generated ChatGPT,

Der SuSI Summit 26 – Sustainable Semiconductor Innovations Summit – ist eine eintägige hochrangige Konferenz, die sich der Förderung von Nachhaltigkeit entlang der gesamten Halbleiter-Wertschöpfungskette widmet. Nach einer erfolgreichen ersten Ausgabe bringt der Summit 2026 am Infineon Campeon in Neubiberg / München führende Vertreterinnen und Vertreter aus Industrie, Verbänden, Wissenschaft und Politik aus ganz Europa zusammen.

Die Bavarian Chips Alliance unterstützt die Veranstaltung als Kooperationspartner.

Unter dem Motto „Exploring ways to Chiptainability“ präsentiert der SuSI Summit 26 zukunftsweisende Ideen rund um nachhaltiges Chipdesign, CO₂-Reduktion, Twin Transformation und Kreislaufwirtschaft. Als bewährtes Spillover-Event für IPCEI ME/CT bietet er eine fokussierte Plattform für fachlichen Austausch, Zusammenarbeit und praxisnahe Lösungen.

Der Veranstaltungstag spannt den Bogen von Innovation, Materialien und Fertigung bis hin zur digitalen Transformation. Im Mittelpunkt steht die Frage, wie die Halbleiterindustrie Nachhaltigkeit zu einem konkreten, messbaren Vorteil macht.

Von der Verzahnung digitaler und grüner Strategien über den Weg vom reinen CO₂-Reporting hin zu echter Emissionsreduktion zeigen die Sessions praxisnahe Ansätze für transparentere, resilientere und emissionsärmere Lieferketten. Darüber hinaus erhalten Sie Einblicke in nachhaltige Materialien, sauberere Produktionstechnologien und intelligente Fertigungslösungen, die Abfall reduzieren und gleichzeitig die Ausbeute verbessern.

Gemeinsam zeigen diese Perspektiven: Nachhaltigkeit ist längst keine parallele Zusatzaufgabe mehr, sondern ein zentraler Treiber für Leistung, Wertschöpfung und langfristige Wettbewerbsfähigkeit.

Nach Ihrer Teilnahme am SuSI Summit verfügen Sie über:

  • ein klares Verständnis aktueller Best Practices und zukünftiger Trends in verschiedenen Bereichen nachhaltiger Halbleiterfertigung,
  • konkrete Einblicke in neue Technologien und innovative Lösungen, die Nachhaltigkeit in der Chipfertigung vorantreiben,
  • wertvolle Kontakte zu Branchenführern, Start-ups und politischen Entscheidungsträgern,
  • praxisrelevantes Wissen zu regulatorischen Entwicklungen, die Ihre strategischen Entscheidungen direkt beeinflussen.

 

Die Veranstaltung findet auf Englisch statt.

Führungskräfte und Entscheiderinnen und Entscheider:
Gewinnen Sie strategische Einblicke in Nachhaltigkeitstrends, die die Halbleiterfertigung prägen.

Ingenieurinnen, Ingenieure und Forschende:
Entdecken Sie innovative Technologien und Ansätze für nachhaltige Produktion und nachhaltiges Design.

Politische Akteure und Regulierungsbehörden:
Erhalten Sie Einblicke in wichtige politische Entwicklungen und regulatorische Rahmenbedingungen, die den Halbleitersektor beeinflussen.

Investoren und Stakeholder:
Erkunden Sie Investitionsmöglichkeiten und vernetzen Sie sich mit zentralen Akteuren der Branche, die Nachhaltigkeit in der Halbleiterindustrie voranbringen.

08:00 Uhr

Morning Coffee und Akkreditierung

Corinna Wolf
Infineon

Stefan Wunderer
Nokia

09:00 Uhr

Begrüßung und Eröffnung des SuSI Summit 2026

Innovation Paths

09:30 Uhr

"Chiptainability: Driving Sustainable Innovation across AI and 6G"

Subho Mukherjee
VP of Sustainability, Nokia

09:50 Uhr

"Moving towards sustainable electronics through twin transformation"

Speaker to be announced
Infineon

10:10 Uhr

"Sustainable Business Innovations"

Henning Breuer
Innovation Consultant, Professor & Author, uxberlin.com

10:30 Uhr

Coffee & Exhibition & Networking

Technology Paths

11:15 Uhr

"Molybdenum and Tungsten for a Greener Semiconductor Future: Plansee’s Path to Sustainable Materials"

Dr. Christoph Adelhelm
Business Development Manager EUV, Business Devision Electronics, Plansee

11:35 Uhr

"Enabling Low‑Emission Polysilicon Etching: NOx Reduction via DeNOx Technology"

Sebastian Liebischer
Innovations Manager Semi Products, Wacker

This work presents an integrated DeNOx approach to enable low‑emission polysilicon etching operations. A key challenge in silicon etching arises from batch‑wise immersion and removal of silicon from the etching solution, which induce highly dynamic process conditions and sharp NOx concentration gradients in the exhaust gas. These transients place significant demands on downstream abatement systems. To address this, advanced real-time NOx measurements were implemented upstream of the DeNOx catalyst, enabling fast response times and high‑resolution monitoring of rapidly changing emission profiles. Catalyst operation was further optimized through improved gas mixing, ensuring uniform flow distribution and full utilization of the active catalyst surface. In parallel, an enhanced control concept, including Advanced Process Control (APC), was deployed to proactively manage load changes and stabilize catalyst performance under dynamic conditions. The combined measures resulted in a substantial and sustained reduction of NOx emissions while increasing etching productivity, demonstrating a scalable pathway toward environmentally optimized polysilicon manufacturing.

11:55 Uhr

"From Scrap to Savings: VisionIQ for Sustainable Semiconductor Yield"

Dr. Thomas Bauer
AI Lead Manufacturing (Semiconductor), ams Sensors Germany GmbH (OSRAM)

Semiconductor manufacturing faces increasing pressure to improve yield, reduce scrap, and lower its environmental footprint—while managing growing process complexity and data volumes. VisionIQ addresses this challenge by introducing a scalable, AI‑driven vision framework that transforms image‑based inspection data into actionable production insights.

The approach moves beyond isolated, rule‑based vision solutions toward a unified architecture for AI image classification across multiple process steps and equipment types. By detecting subtle defect patterns earlier and more consistently, VisionIQ enables faster root‑cause analysis, targeted process adjustments, and a measurable reduction of scrap and rework.

This talk presents the VisionIQ concept from a manufacturing perspective: how standardized data ingestion, model governance, and production‑ready deployment allow AI vision to scale sustainably in high‑volume semiconductor environments. Real‑world learnings from frontend manufacturing illustrate how VisionIQ contributes not only to yield improvement and cost savings, but also to resource efficiency and long‑term sustainability in semiconductor production.

12:15 Uhr

"Green is Black: Maximizing Value from Concept to Circularity"

Luca Fontanella
Sustainability Champion, ST Microelectronics

Abstract

 

Integrated sustainability embeds environmental and social criteria into every step of the value chain—from technology and product conception, through manufacturing and use, to reuse and recycling—while systematically tracking economic impact. By designing products for energy efficiency, durability, repairability, and recyclability, companies reduce material and energy consumption, limit waste, and diminish regulatory and reputational risks. In manufacturing, resource optimization, process efficiency, and responsible sourcing translate directly into lower operating costs and more resilient supply chains. At end of life, strategies such as remanufacturing, component harvesting, and closed-loop recycling recover material and functional value that would otherwise be lost. When these actions are coordinated within a circular business model, the cumulative effect is clear: over the full lifecycle, sustainable design and operations generate more gains than losses and more income than spending—through cost savings, new revenue streams, risk reduction, and enhanced brand and market positioning.

12:35 Uhr

Lunch & Exhibition & Networking

Carbon Reduction Paths

13:35 Uhr

"From Carbon Reporting to Carbon Reduction: How Agentic AI Is Rewiring Semiconductor Supply Chains"

Payal Shah
Co-Founder, NeoNetra

13:55 Uhr

"Semiconductor Sustainability beyond green electricity"

Dr. Wolfgang Nüchter
Mobility Electronics, Operational Sustainability Officer, Bosch

The increasing use of green electricity is a key lever for reducing the carbon footprint of semiconductor manufacturing, but it does not eliminate all relevant environmental impacts. This paper analyzes the effect of green electricity on the corporate footprint of Bosch and illustrates the impact at product level using a MEMS device as an example. A comparison of scenarios with and without green electricity highlights the significant reduction potential, while also revealing remaining contributors such as process gases, abatement efficiency, and consumables.

Going beyond climate change mitigation, the paper extends the perspective to biodiversity impacts, focusing on material origin and supply chains for critical raw materials such as gold and platinum group metals. The analysis shows that further progress requires increased use of recycled precious metals, improved abatement technologies, and the development of alternative process gases. These measures are essential to achieve a more comprehensive sustainability transformation of semiconductor manufacturing.

14:15 Uhr

"Milliwatts at Scale  - Power Optimization and the CO₂ Footprint in the ASIC Design Process"

Richard Willems
Swissbit

14:35 Uhr

"Assured and Auditable: Product Carbon Footprints that Survive Real Scrutiny"

Stephen Russell
Senior Technical Fellow - Sustainability, TechInsights

Sustainability claims in semiconductors increasingly fail not on intent, but on whether a footprint can be reproduced, compared, and defended under audit. Using EcoInsights workflows, we will show how to generate ISO 14067-aligned PCFs, along with an audit pack that includes assumption registers, sensitivity tests, and traceability artifacts suitable for customer procurement and third-party review.

A deep-dive case study will connect assurance discipline to architectural design decisions in advanced packaging: comparing two die-stack options where a seemingly small choice, such as selecting a 2GB versus 3GB DRAM die, materially shifts the packaged device PCF through die area, yield, and packaging contributions. We will show how boundary and allocation choices can exaggerate or mask that design impact, and how standardization and assurance controls restore decision-grade comparability, enabling engineering and procurement teams to make defensible “twin transformation” trade-offs.

14:55 Uhr

Coffee & Exhibition & Networking

Collaboration Paths

15:30 Uhr

World Café / Infineon Tour

16:20 Uhr

World Café Panel

16:50 - 17:00 Uhr

Closing of the SuSI Summit 2026