PlanV GmbH

Our current projects involve developing a

• low-latency cache coherence unit for an RISC-V multicore processor and
• hardware acceleration of the robot operating system (ROS) based on RISC-V.

Technology. Made simple

At PlanV, we are a young and motivated team of top-notch engineers who are at the forefront of chip design excellence. Leveraging open-source technologies, we are committed to delivering excellence in every aspect of our work.

• Development, customization, verification and integration of RISC-V CPUs
• Development, customization, verification and integration of IPs
• FPGA prototyping
• ASIC development
• Selecting, validating and integrating the most suitable components and tools for our customers' designs and workflows
• Technical management, CTO as a service

• ASIC development
• FPGA development
• RISC-V and computer architecture